Delta- Sigma Modulator with Signal Dependant Feedback Gain

Higher order Delta-Sigma Modulator (DSM) is basically an unstable system. The approximate conditions for stability cannot be used for the design of a DSM for industrial applications where risk is involved. The conventional second order, single stage, single bit, unity feedback gain , discrete DSM cannot be used for the normalized full range (-1 to +1) of input signal since the DSM becomes unstable when the modulus of the input signal is above 0.55. The stability is also not guaranteed for amplitude of input signal less than 0.55. In this proposal, the conventional second order DSM is modified with input signal dependant feedback path gain. The proposed DSM is suitable for industrial applications where one needs the digital representation of the analog input signal, during each sampling period. This first configuration of proposed DSM can operate for the full range of input signal without causing instability. In order to improve the SNR of first configuration, it is combined with conventional second order DSM and proposed the second configuration of DSM. I. INRODUCTION In the conventional discrete second order DSM [1],[2] and [3] the sampling of input signal and DSM operation is performed by single clock signal with period TC and is shown in Fig.1. The block D is the delay unit of one clock period (TC) and the block Q is binary quantizer. In Fig.1, x(i), x1(i), x2(i) and y(i) represent the i sample of input signal, first integrator output, second integrator output and quantizer output respectively. The quantization error signal during i sampling period is denoted as e(i). Fig.1 Conventional Second-Order DSM The difference equation governing the second-order DSM, is given by, Y(i) = x(i) + e(i) -2e(i-1) +e(i-2) (1) The average value of the digital output during update period TU (TU >>TC) , is equal to the average value of the discrete input signal during the same period. The DSM becomes unstable when the modulus of the input signal is above 0.55. In [4] is proposed a method for achieving adaptive reduction in the order of the loop filter of usual high-order, single-stage, single-bit DSM in order to improve the stability range and SNR. The resulting DSM recovers from instability, with extended input range when compared to the corresponding conventional DSM but the SNR starts falling down when the input signal amplitude exceeds 0.55. According to [1] and [5] loop stability is obtained by feed forward coefficients and feedback coefficients and are added to optimize quantization noise response in base band. By using multiple feed forward and feedback features into second order structure, more flexibility is obtained for improving stability and improving dynamic range. In the research papers [6] and [7] is proposed a single-loop DSM with extended dynamic range. It employs an auxiliary quantizer to process the quantization error of the main quantizer. This simple addition guarantees improved stability over a wider signal input range and also reduces the sensitivity to the front-end DAC nonlinearity. K.Diwakar et al. / International Journal of Engineering and Technology (IJET) ISSN : 0975-4024 Vol 7 No 1 Feb-Mar 2015 205 In [8] is proposed Sturdy MASH (multi-stage noise shaping) DSM which provides reduced sensitivity to circuit non-idealities but not stable for the full range of input signal. The Sturdy MASH becomes unstable when the input signal is around -2dB. In [9] is proposed Mixed order sturdy MASH DSM which also provides better reduced sensitivity to circuit non-idealities but becomes unstable when the input signal is around -3dB. Pui-Kei Leong et. al. in [10] describes the design and implementation of low power Delta-Sigma digital pulse width modulation controller for switching converters which can operate at high frequency. Smaller quantizer with a limiter is used in the digital Delta-Sigma modulator to minimize the area consumption. The resulting SNR after implementation is decreased when the input amplitude is higher than 0.9FS. Jiaxin Ju et. al. in [11] presented a low voltage switching capacitor DSM and focused on the implementation of unity gain and conventional DSM which could reduce the requirement of operational amplifier DC gain and was able to reduce the circuit complexity, power consumption and area. However, the SNR falls when the normalized input signal exceeds -3dB. In the research paper [12] is proposed single-loop DSM with extended dynamic range which provides spurious free dynamic range of 87.5dB. In [13] is presented, describing function approach to study the overload of multibit quantizer. For dc signal, when the magnitude of input is greater than 0.8, the DSM becomes unstable. In the present proposal, the proposed DSM can function for the full range of input signal. The input signal can be dc or sine signal. In [14] is proposed an approach to find the modulator which maintains its performance like stability, SNR etc. against the parasitic effects. The SNR falls when the input is around -3dB. In the present proposal, the SNR never falls after certain range of input signal. The SNR increases steadily for the full range of input signal. Two configurations of DSMs are proposed (DSM1 and DSM2). In the proposed DSM1, the demodulated signal closely follows the sampled analog input signal for the entire normalized range -1 to +1. The maximum value of the error signal is 0.8mV (0.08%). The SNR never falls after certain range of input signal. The SNR steadily increases and reaches the maximum value at Full scale. In the power spectral density (PSD) the noise level is much below the signal level and so the noise can be easily filtered out from the signal. The second configuration DSM2 is the combination of DSM1 and conventional DSM. In DSM2, the SNR is maximized for the entire range. II. BLOCK DIAGRAM OF PROPOSED DSM OF CONFIGURATION 1 (DSM1) The block diagram of the proposed second order DSM1 is shown in Fig.2. The sample and hold circuit S/H1 samples the input signal at a sampling period TC and is denoted as (x)TC. (x)TC is fed to the input of DSM. The S/H2 circuit samples the input signal at a sampling period TU and is denoted as (x)TU. The feedback gain is n×(x)TU (n>1). In [14] the input signal fed to the DSM is dc being it is sampled at TU. In this proposal, the input signal is sampled at TC as in the case of conventional DSM, the operating period of DSM2 is proportional to (x)TU and the DSM circuit is operating at TC. Fig. 2 Proposed DSM1 with signal dependant feedback gain K.Diwakar et al. / International Journal of Engineering and Technology (IJET) ISSN : 0975-4024 Vol 7 No 1 Feb-Mar 2015 206 During each update period, the bit stream at the output of quantizer gives the digital representation of input signal. The average value of bit stream at the output during each update period is equal to the average value of sampled input signal. The normalized value of y (ny) is equal to the normalized input signal (x/n). In the proposed DSM, the output of first summing unit is equal to (x)TC n×(x)TU ( if y(k)=1) and this quantity is much less than the output of first summing unit in the conventional DSM ((x)TC-n). This fact makes the outputs of the integrators much less. The proposed modulator increases the input signal range to full scale. The upper bound of the state variable x2 never overloads the quantizer and hence the proposed DSM is stable for the complete range of the input signal. The dynamic range, SNR in the higher range and PSD are better than the conventional DSM and DSMs proposed in the referred papers. A. Relation between Input and Output in the Proposed DSM1 The operating time, TO of the DSM circuit during each update period is varied proportional to x x TU = | ) ( | .Therefore,